Prior art type microprocessors are less than ideally suited for certain kinds of applications. Consider, for example, some of the operations performed in calculating a discrete, fast Fourier transformation (FFT) of the type commonly used in spectrum analysis. In what is commonly referred to as a "butterfly" certain operations are performed (four multiplications usually performed in parallel) followed by four additions or subtractions (also usually performed in parallel) during a total of at least two clock cycles on a first parameter before the first parameter is combined with (added to or subtracted from) a second parameter. Fetching the two parameters from memory at different times is undesirable in that it is inconsistent with high speed operations and it requires additional logic. Holding the second parameter, such as by holding a clocking signal, is undesirable. This is because it is inconsistent with high speed operation, requires additional logic, and requires the use of multiple clocks. Also, to reduce the number of computations required, certain discrete, fast Fourier transformation operations require that certain parameters (samples) be addressed in what is commonly referred to as a "bit-reverse order". Further, the "rounding off" of certain results is required in order to maintain accuracy. For additional information on discrete, fast Fourier transformation operations, the reader is referred to the application note by Julie Lin and Danh Le Ngoc which is designated AN-XX High Performance Fixed Point Fast Fourier Transformation Processor (10-14-1988) by Integrated Device Technology, Inc.
The prior art type device which is designated 7381 by Integrated Device Technology, Inc., L4C381 by Logic Devices, Inc., and S614381 by Gould, Inc., includes an "A" and a "B" input register, an "A" multiplexer configured with one set of multiplexer data inputs connected to the data inputs of the "A" register and with another set of multiplexer data inputs connected to the data outputs of the "A" register; a "B" multiplexer configured with one set of multiplexer data inputs connected to the data inputs of the "B" register and with another set of multiplexer data inputs connected to the data outputs of the "B" register; an "R" multiplexer, configured with one set of multiplexer data inputs connected to the data outputs of the "A" multiplexer, and an "S" multiplexer configured with one set of multiplexer data inputs connected to the data outputs of the "B" multiplexer. In addition, the device includes a 16-bit arithmetic logic unit configured with one set of unit data (operand) inputs connected to the data outputs of the "R" multiplexer and with another set of unit data (operand) inputs connected to the data outputs of the "S" multiplexer. Further, the device includes an "F" output register configured with the register data inputs connected to the data outputs of the arithmetic logic unit, an "F" multiplexer configured with one set of multiplexer data inputs connected to the data inputs of the "F" register and with another set of multiplexer data inputs connected to the data outputs of the "F" register, and a tri-state output driver unit configured with the unit data inputs connected to the data outputs of the "F" multiplexer. Unfortunately, the device lacks means for "delaying" a parameter, means for "bit-reverse order" addressing, and means for "rounding off" certain results.